J-K Flip-Flops

2001 >> 10/02/2023

To avoid some of the confusion that may exist on the "Logical Clocking" and the methods of "Data-Capture" and "Data-Transfer" ("Master/Slave") on a variety of J-K / F-F's, I would like to suggest this approach:

Initial Considerations

  1. The J-K Flip-Flop goes well beyond the basic Flip-Flop or Data-Latch, in that there are Logic Controls for Data-Inputs (i.e.the "J" & "K"), associated with the Clock, sometimes called a Trigger.
  2. A J-K Flip-Flop may or may not have a method of "Direct-Set", also called "Preset" (or simply "SET"), which forces the device into "Q" high, regardless of any logical data input or clocking. This input overrides logic controls.
  3. In the same respect a J-K Flip-Flop may or may not have a method of "Direct-Reset", also called "Clear" (or simply "RESET"), which forces the device into "/Q" high, regardless of any logical data input or clocking. This input overrides logic controls.
  4. As in a number of simple "Data-Latches", if both Set and Reset are applied simultaneously, the so-called "Illegal-Condition" will occur, with both Q and /Q going active high at the same time. In a designer's point of view, there may be a situation where this is actually desired, for a special initial function.
  5. There are two general catagories of J-K Flip-Flops, where the most basic version will present the resultant logical data inputs immediately to the respective outputs when triggered or clocked. The 2nd version can be actually considered as two JK FF's in a single device, where the logical inputs are first "Captured" during one phase of the clock, and "held" in state, and then "Transferred" to the output of the second device during the "Transfer" phase of the clock.
  6. The method of "Capture & Transfer" events on a respective clock cycle may be by "Level-Capture" or "Edge-Capture" (+/- Edge), and then passed to the output by similar fashion. It is important for the designer to understand which method/action is incorporated for the respective device in use.
  7. Here are breadboard examples (PDF) of a "Level-Capture and Transfer" J-K Flip-Flop,versus a "Edge-Capture and Transfer" J-K Flip-Flop, to show how these actions occurs.
  8. I have found both of these two circuit examples very helpful in the classroom for those who were having conceptual difficulties, and were then able to properly incorporate respective TTL devices properly in future design implementations.
  9. As a general rule, the J & K Logical Inputs are AND Gates, and may be Logic-High or Logic-Low configurations. You may very well encounter where multiple Logic-Inputs are in employed, and basic gating considerations would be dealt with accordingly.

Logic Considerations

  1. The Logic-Input function inputs should be treated as any common AND Gate, as in "Enable" vs "Inhibit" Inputs, to "Activate" the respective gate.

    i.e. If the J or K inputs are Low, there will be no Logic-Data transferred when the clock occurs. An exception to this is when the Logic-Input to the respective Logic-Control requires a Low (as in the 74109 series).

  2. If the "J" Data Input is "Enabled" and the "K" Data Input is NOT "Enabled", then the Flip-Flop will "Set", with Q going high, and /Q going low.
  3. If the "K" Data Input is "Enabled" and the "J" Data Input is NOT "Enabled", then the Flip-Flop will "Reset", with /Q going high, and Q going low.
  4. If both the "J" and "K" Data Inputs are "Enabled", then the Flip-Flop will normally "Toggle" from it's previous state to the opposite state.
  5. With a "Master/Slave" version, there is a considerable advantage available for first "Capturing" the current state of data, holding it for some period of time, and then "Transferring" it at a desired moment.