For the TTL inputs, is the "undefined region" split evenly between the lower half and the upper half?
"Undefined Region" of TTL inputs
For the CMOS inputs, is the "undefined region" split evenly between the lower half and the upper half?
"Undefined Region" of CMOS inputs
For the TTL outputs, does the "high" come anywhere close to the +5V? How "low" is low?
TTL outputs as "high"
TTL outputs as "low"
Are the CMOS outputs really any different than the TTL outputs? If so, in what way?
CMOS outputs as "high"
CMOS outputs as "low"
How might the "outputs" of one gate match up with the input margins of another gate?
Gate outputs fed to other Gate inputs (loads & margins)
Are the CMOS outputs "compatible" with the TTL inputs, and vise-versa?
Gate outputs of CMOS vs TTL outputs
Are the "HC" and "HCT" more, or less, "compatible" with TTL?, or with each other?
Other "Family" compatibility
Do the different TTL Families have the same "Fanout" within their respective group?
"Fanout" comparisons for numerous TTL Families
Do CMOS gates have the same "Fanout" as TTL?
"Fanout" comparisons of CMOS vs TTL
There are two areas of "current or power" to be concerned with:
Power requirements of different "Families"
Gate input requirements. ----
"More than just highs & lows"
Why, or how would that be so?
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Thresholds.html - SfE-DCS, ddf - 07/20/2001 Threshld.sam -- AmoPro -- ddf -- 06/15/98