## A Unique Approach to Digital Gates:

09/02/2001

Initial Digital Gate Concepts:

Gate Conversion Techniques:

"Forced" vs "Maybe" Conditions:

Dynamic Signal Analysis of Gate Outputs as a result of Gate Inputs:

Gate Enabling:

Gate Inhibiting:

Coincident-Gating of Multiple-Data-Inputs:

Coincident-Gating of Multiple-Data-Inputs and Multiple-Controls:

Gate Thresholds:

### Initial Digital Gate Concepts:

Most textbooks present the basic concepts of "0" & "1" inputs, using a Truth-Table to indicate the output results.

### AND Gate

 X Y Z 0 0 0 0 1 0 1 0 0 1 1 1

### OR Gate

 X Y Z 0 0 0 0 1 1 1 0 1 1 1 1

Forget the "0's" and "1's" approach for now!! ..... Because there's ....

#### The "Only" Gate:

Even though that method has been the "Standard" for many years, and does illustrate the basic concept of when either the AND Gate or the OR Gate is active, it is extremely cumbersome when it comes time to evaluate either of those gate conditions. This is especially true when there are multiple inputs to deal with. Here we only have 4 conditions, due to the fact that there are only 2 inputs (i.e. 22=4 possible states), but if we have 3 inputs (i.e. 23=8 possible states) or 5 inputs (i.e. 25=32 possible states) a truth-table gets unwieldy in a hurry. What if we had an AND Gate with 9-Inputs? Not only would that require a Truth-Table with 512 possibilities, the evaluation process for those variables becomes ...... Well, you get the picture!

Consider this simple fact about an AND Gate. No matter how many inputs there are, there is actually only "ONE" possible condition for an active gate. I suggest the nickname: "The ONLY Gate", because there is only that one time, out of all those possible combinations that the AND Gate will go active. Now we're suddenly making things much simpler and therefore much easier.

#### The "Any" Gate:

Now consider this simple fact about an OR Gate. No matter how many inputs there are, the gate will go active ANY time ANY one of the control inputs meet the right state or condition. You should be able to see why I suggest the nickname "The ANY Gate", because of those multitude of input possibilities that can make that gate go active.

Now, are you ready for this? If you look closely at what we have just said, and compare all of those possibilities of the OR Gate input controls, vs what it will take to make the OR Gate go active, you will see that it is a mirror image of the AND Gate!!

Think of it this way, even with the OR Gate, there is ONLY ONE TIME that the OR Gate will NOT go active, out of all those possiblities of input controls! Consider what I'm saying here, in that you can simply convert an OR Gate to an AND Gate, by considering the Mirror Image of the original gate.

Here I want to propose a new rule, but I need to present something else first:

#### Here's how that works:

Gates of any kind, may show an Inverter in one of the input lines of the gate as either in the shape of an Inverter, or it may more often as not, illustrate the presence of an Inverter or Inversion Process, as a small circle, called a "Bubble". This Inverter, or Inversion Process, simply converts an incoming ""high" to a "low" (i.e. a "1" to a "0"). The same may be true of a gate output to illustrate an Inversion Process there as well.

When you see a 'Bubble', think 'Low'

Suppose that we have a 2-Input AND Gate where both of the inputs involve that Inversion Process. Using the normal textbook approach, we would be told that we need to treat those inputs one at a time, using a Truth-Table to analize the results with "1's & 0's". Well, that's ok if we want the confusion factor in play, but how about an extremely simple way instead?

A very simple method of dealing with this situation, is to treat those bubbled inputs as "Lows", both of which are required to make that AND Gate go active. I.e "ONLY when BOTH inputs are Low", will that AND Gate go active. Hmmm....

Now suppose a more complicated situation (actually it's not, it only seems that way at first) where with the 4-inputs ABCD are non-inversion, inverted, non-inversion, and inversion respectively on those ABCD inputs. With a Truth-Table, you would have to look at all those 16 possiblities for the "1's and 0"s" relationships. Ah, but remember that an AND Gate is in reality an "ONLY Gate", with ONLY One Time that the AND Gate will go active out of all 16 possibilities. That will only happen when A=1, B=0, C=1, and D=0 (i.e. when A is high, B is low, C is high, and D is low). If you remembered to "think low when you see a 'Bubble' ", this would been a snap to do! This always works, and is sure easy to remember. One more consideration, and that is that if that same AND Gate had a bubble on the output it would simply mean that the output of the gate will go low, when the gate goes active. What could be easier? If you really want to be a whiz at quickly analizing static gate combinations, this far beats the "1's and 0"s" approach.

#### Gate Conversion Techniques:

Consider what was said earlier about the OR Gate results being a Mirror Image of the AND Gate, and also remembering to consider what has been said about the "Bubble" inputs and outputs, we will be able to do something quite remarkable (and besides, it's quite easy to do as well). Take either an AND Gate or an OR Gate, and simply take any input that is non-inverted, and make it inverted. In the same manner, take any inverted input and make it non-inverted. Likewise, if the output is inverted, make it non-inverted, and if it's non-inverted, make it inverted. Now, if the gate is an AND Gate, change it to an OR Gate, and if it's an OR Gate, change it to an AND Gate. The result is that "If you change everything, you haven't changed anything", except for just the appearance!! Your previous AND Gate will now look like an OR Gate, but with all inputs/outputs inverted. In that same respect, your previous OR Gate will now look like an AND Gate, but with all inputs/outputs inverted.

There's our new rule, and it always works, even with complicated gates!

Yet, we have not really changed the action of our gate, only the way it looks. So why do this? Well, for an example, it allows us to easily evaluate what starts out as an OR Gate to now be evaluated as an AND Gate (remember that it can be best thought of as an "ONLY Gate"), so now we only have to look for that one condition that will allow the gate to go active. If you think about how easy it now can be to bounce back and forth between the way we look at either AND/OR Gates, where we can realize that one is always the mirror image of the other.....

Unfortunately, most of the textbooks only take a very brief or passing look at this very helpful technique.

#### "Forced" vs "Maybe" Conditions

We can make some other interesting observations on the AND Gate vs the OR Gate. Starting with a 3-input AND Gate, with all 3 inputs as non-inverting, we find that there are basically 8 possible combinations. We can also make a startling discovery (you know, one of those that becomes obvious once we see it) where we can note that if ANY one of those 3 inputs is taken low, it "kills" the gate. That simply means that if any one input is taken low, will disable that gate, no matter what the other line combinations are. I would propose that we call this a "Forcing Condition", because it forces that gate into an inactive state regardless of any other input control line conditions.

Now, another consideration is that just because we take any one of those input lines high, that will not in itself cause any gate activity. In fact, even if we took any two of those 3 lines high, we would still not activate that gate. With those two considerations, I would propose calling these "Maybe Conditions", because each of those situations are in fact, a condition of "Maybe" the other line(s) will go high and allow our gate to go active (i.e. "Maybe they will", and "Maybe they won't").

These two opposite input control conditions allow us to see those gate control inputs in a little different light, in that when any one control line input establishes a condition of "no-go", why pursue the other input lines? In that same respect, when one input line satisfies a possibility, we must pursue the other possibilities.

#### Static vs Dynamic Considerations: I.e. Signal Analysis of Gate Outputs as a result of Gate Inputs:

Truth-Tables and the previous methods that were previous outlined, are good for "Static Signal Conditions", where things are not rapidly changing on us, but what about conditions where the signals are those that you can only see with an oscilloscope or such? Those conditons are called "Dynamic Signals", and here are some methods for dealing with them. These following explanations, by their very nature appear at first to be a "play on words", but hopefully you will soon see that there is a "method to my madness" here, and it works!

### Key Points:

#### Active States:

• The Gate must either be Enabled with a High on the Control-Leg,
• or NOT Inhibited by using a Low on the Control-Leg.

#### Data Output:

• The Data Output will only follow the Input Data if the gate is active.
• The Data will be inverted if there are an odd number of Inverters in that data path.

#### Resting States:

• The "Resting State" of the output of the gate is always based on the gate NOT active.
• Non-inverted outputs always "Rest Low", whereas inverted outputs always "Rest High".

### Gate Enabling:

#### Example #1:

Show pdf view (~45Kb)

Consider a 2-input AND Gate, where the first input is used for a dynamic signal input on that data-line, and the second input is "dog-legged" down as a "Control-Leg" that can be used to Enable the Gate. At first this might seem in conflict with what was presented ealier about AND Gates, but let's present a new concept.

When the Control-Leg is High (Enabling the gate), and the data-line is Low, the output will be Low. Now, if the data-line goes High, the output will also go High. The important observation here is that the output will follow the data-input when the gate is enabled. When that Control-Leg is Low, the gate is NOT Enabled, and now the gate output will always be low regardless of what we do on that data-input line, and cannot possibly follow that input signal. I propose that we call this non-active state a "Resting State", that Rests Low when not Enabled.

Example #2:

Show pdf view (~45Kb)

Consider again a 2-input AND Gate, where as before, the first input is used for a dynamic signal input on that data-line, and the second input is "dog-legged" down as a "Control-Leg" that can be used to Enable the Gate with a High. Now in this case, we will invert the output (or use a NAND Gate), which will allow the same kind of input controls as Example #1, but the output will be an inversion of the data-signal input. I.e. the important observation here is that the output will follow the inversion of the data-input when the gate is enabled. Secondly, when that Control-Leg is Low, the gate is NOT Enabled, and now the gate output will always be high regardless of what we do on that data-input line, and cannot possibly follow that input signal. I propose that we call this non-active state a "Resting State", that Rests High when not Enabled.

Example #3:

Show pdf view (~45Kb)

Consider again a 2-input AND Gate, where as before, the first input is used for a dynamic signal input on that data-line, and the second input is "dog-legged" down as a "Control-Leg" that can be used to Enable the Gate with a High. Now in this case, we will invert the input, which will allow the same kind of input controls as Example #1, but the output will be an inversion of the data-signal input. I.e. the important observation here is that the output will follow the inversion of the data-input when the gate is enabled. Secondly, when that Control-Leg is Low, the gate is NOT Enabled, and now the gate output will always be low regardless of what we do on that data-input line, and cannot possibly follow that input signal. I propose that we call this non-active state a "Resting State", that Rests Low when not Enabled. Note that during the time that the gate is active, the signal output is like Example #2 in that the output follows the inversion of the input, BUT the output rests low when not enabled.

#### Example #4:

Show pdf view (~45Kb)

Consider a 2-input AND Gate, where the first input is used for a dynamic signal input on that data-line, and the second input is "dog-legged" down as a "Control-Leg" that can be used to Enable the Gate. This is like Example #1, EXCEPT that both the data-input line is inverted, and so is the gate output. I.e. this will cause a double-inversion of output to input.

When the Control-Leg is High (Enabling the gate), and the data-line is Low, the output will be Low (because of that double-inversion). Now, if the data-line goes High, the output will also go High (for that same reason). The important observation here is that the output will follow the data-input when the gate is enabled. When that Control-Leg is Low, the gate is NOT Enabled, and now the gate output will always be low regardless of what we do on that data-input line, and cannot possibly follow that input signal. I propose that we call this non-active state a "Resting State", that Rests Low when not Enabled.

### Gate Inhibiting:

#### Example #1:

Show pdf view (~45Kb)

Consider a 2-input AND Gate, where the first input is used for a dynamic signal input on that data-line, and the second input is "dog-legged" down as a "Control-Leg" that can be used to Inhibit the Gate. An exception to the use of the Control-Leg as an Enable, is that as an Inhibit, that Control-Leg is Inverted. Where the Enable required a High to Enable the gate, here a High will cause an Inhibit. Although some folks might argue that it's all the same thing, I strongly disagree. We commonly use such expressions in our daily life that we do not consider as simply a moot point. A case in point: We may ask someone the question "is the motor off?", v.s. "is the motor on?" implies very directly a different issue. Simply answering "yes" to these improperly, could meet with bad results for someone. The point here, is that where we commonly use either of these two expressions in every day life with proper applications, and think nothing of it. Unless someone missunderstands us!

When the Control-Leg is Low (NOT Inhibiting the gate), and the data-line is Low, the output will be Low. Now, if the data-line goes High, the output will also go High. The important observation here is that the output will follow the data-input when the gate is Not Inhibited. When that Control-Leg is High, the gate is Inhibited, and now the gate output will always be low regardless of what we do on that data-input line, and cannot possibly follow that input signal. I propose that we call this non-active state a "Resting State", that Rests Low when Inhibited.

Example #2:

Show pdf view (~45Kb)

Consider again a 2-input AND Gate, where as before, the first input is used for a dynamic signal input on that data-line, and the second input is "dog-legged" down as a "Control-Leg" that can be used to Inhibit the Gate. Now in this case, we will invert the output, which will allow the same kind of input controls as Example #1, but the output will be an inversion of the data-signal input. I.e. the important observation here is that the output will follow the inversion of the data-input when the gate is NOT Inhibited. Secondly, when that Control-Leg is High, the gate is Inhibited, and now the gate output will always be high regardless of what we do on that data-input line, and cannot possibly follow that input signal. I propose that we call this non-active state a "Resting State", that Rests High when Inhibited.

Example #3:

Show pdf view (~45Kb)

Consider again a 2-input AND Gate, where as before, the first input is used for a dynamic signal input on that data-line, and the second input is "dog-legged" down as a "Control-Leg" that can be used to Inhibit the Gate. Now in this case, we will invert the input, which will allow the same kind of input controls as Example #1, but the output will be an inversion of the data-signal input. I.e. the important observation here is that the output will follow the inversion of the data-input when the gate is NOT Inhibited. Secondly, when that Control-Leg is High, the gate is Inhibited, and now the gate output will always be low regardless of what we do on that data-input line, and cannot possibly follow that input signal. I propose that we call this non-active state a "Resting State", that Rests Low when Inhibited. Note that during the time that the gate is active, the signal output is like Example #2 in that the output follows the inversion of the input, BUT the output Rests Low when Inhibited.

#### Example #4:

Show pdf view (~45Kb)

Consider a 2-input AND Gate, where the first input is used for a dynamic signal input on that data-line, and the second input is "dog-legged" down as a "Control-Leg" that can be used to Inhibit the Gate. This is like Example #1, EXCEPT that both the data-input line is inverted, and so is the gate output. I.e. this will cause a double-inversion of output to input, providing that the gate is NOT Inhibited.

When the Control-Leg is Low (NOT Inhibiting the gate), and the data-line is Low, the output will be Low (because of that double-inversion). Now, if the data-line goes High, the output will also go High (for that same reason). The important observation here is that the output will follow the data-input when the gate is NOT Inhibited. When that Control-Leg is High, the gate is Inhibited, and now the gate output will always be low regardless of what we do on that data-input line, and cannot possibly folow that input signal. I propose that we call this non-active state a "Resting State", that Rests Low when Inhibited.

### Coincident-Gating of Multiple-Data-Inputs:

If we have a 2-Input AND Gate, where the 2-Inputs are both Dynamic-Data, then the resulting output will depend on the proper "Coincidence" of those 2 input signals. When they both meet the requirements to make the Gate become "Active", then the Gate-Output will be "Driven High" if the Output is Non-Inverting, or "Driven Low" if the Gate-Output is Inverting.

### Multiple Gate Inputs as Multiple-Data, Multiple-Enables, and Mutiple-Inhibits:

Now, consider that we had a Gate with multiple Data-Signal-Inputs that are "Coincidence-Gated", and also with multiple Control-Legs. The simple fact is that Coincidence-Gating will never even be an issue unless the Gate is made "Active", and the only way this will happen is if any Enables that exist are High, and any Inhibits that exist are NOT high. When the controls allow the Gate to go "Active", then "Coincidence-Gating" of the Data-Input Signals may be in effect.