Digital Labs 1
08/31/2001-- 05/20/2013
The Basics, Part 1 of 6
|
Lab Descriptions |
Theory |
Schematic |
| Basic Gates, and Basic Functions | Theory | |
| "Functions" vs Gates !! | Theory | |
| Thresholds and Outputs | Theory | |
| Basic "Boolean" descriptions | Theory | |
| Gate Conversions | Theory | |
| Connective Gating (NAND's, NOR's) | na | |
| Gating & Control | Theory | |
| "Enable" vs "Inhibit" Controls | Theory | |
| Review of "Forced" vs "Maybe" Input Controls |
Theory | |
| Exclusive OR "Functions" (3 Circuits) Comparator Circuit, Half-Adder Circuit, and The 4 NAND's |
Theory  |
|
| The Exclusive OR Function as a Selectable Inverter | na | |
| Boolean Conversions via "DeMorgan's Law" |
Theory | |
| The RS Data Latches | na | |
| "Flip-Flops",
using Cross-Coupled NAND's & NOR's |
na | |
| "Flip-Flip", v.s. "Illegal" or "Prohibited" | na | |
| "Flop-Flop", v.s."Illegal" or "Prohibited" | na | |
| "Forced" v.s. "Maybe" Input Controls (again, for the RS-FF's) |
na | |
| The 4-Input / 4-Output Exclusive-Or Circuit,
and "Troubleshooting" |
Theory | Schematic |
| Dynamic-Gating Analysis | Theory | Schematic |
Next Digital Lab Pages
- DigitalLabs2 - Connective Gating of NAND's NOR's
- DigitalLabs3 - Exclusive-OR Circuits
- DigitalLabs4 - Data Latches & R-S Flip-Flops
- DigitalLabs5 - J-K Flip-Flop Considerations
- DigitalLabs6 - Timer Circuits - One-Shots/Single-Shots, Free-Running